Nonvolatile flash memory devices store information in the form of charge in a flash cell. A flash cell includes a CMOS transistor with an additional floating metal gate between the substrate and the gate of the transistor. The charge is stored in the floating gate and is injected to the floating gate during an operation known as programming. The charge may be removed during an operation known as an erase operation. As the charge in the floating gate may vary contiguously, it is possible to store more than just one bit per flash transistor by using several charge levels to symbolize different sequences of bits.
FIG. 1A demonstrates a voltage level distribution for a 3 pbc (bits per cell) flash memory cell. The voltage level distribution includes eight lobes 101-108. Each lobe represents a 3-bit value. Each lobe defines a range of thresholds voltages. A threshold voltage that belongs to that range represents the 3-bit value. FIG. 1A illustrates non-overlapping lobes, however this is only schematic, and in practical cases the lobes may overlap. The reason for overlapping may be intentional for obtaining high programming speed, or due to the retention effect. For floating gate devices, an “old” page, may introduce greater overlap between lobes than a new page, since after many program/erase (P/E) cycles there is accumulated trap charge, which is de-trapped over time. After a long duration, every lobe may have a larger standard deviation (std) and may have a different mean location. These effects are also known as retention.
The 3 bit per cell includes a most significant bit MSB (denoted 11 in FIG. 1), a central significant bit CSB (denoted 12 in FIG. 1) and a least significant bit LSB (denoted 12 in FIG. 1). A physical page of flash memory module may store three logical pages. This physical page is programmed one logical page after the other.
The programming includes various types of programming such as MSB programming, CSB programming and LSB programming.
In MSB programming some of the cells are programmed to a single lobe and some are left in the erase state. At the end of the programming process only two lobes exists, the erase and the MSB lobes.
In CSB programming the erase lobe and the MSB lobe are each split into two lobes by further programming pulses, depending on the original state of each cell and the corresponding CSB bit. At the end of this step there are four lobes.
In LSB programming each of the four lobes is further split to create 8 lobes, overall.
The logical pages are read by applying various types of read operations such as MSB read (in which a MSB threshold 114 is used), CSB read (in which two CSB thresholds 112 and 116 are used) and LSB read (in which four LSB thresholds 111, 113, 115 and 117 are used).
Each read operation is applied by providing to the gate of a read cell a reference voltage that equals one of the thresholds.
MSB reading includes supplying to the gate of a read transistor a reference voltage that equals the MSB threshold.
CSB reading includes a first read operation in which the gate is provided with a reference voltage that equals CSB threshold 112 and a second read threshold in which a reference voltage that equals CSB threshold 116 is provided.
LSB reading includes four read operations in which reference voltages that equals each of LSB thresholds 111, 113, 115 and 117 are provided to the gate of the cell.
FIG. 1B demonstrates a voltage level distribution for a 2 pbc (bits per cell) flash memory cell. This voltage level distribution includes four lobes 201-203. Each lobe represents a 2-bit value. In this case there are only one MSB threshold 212 and two LSB thresholds 211 and 213.
As mentioned, the lobe distributions are not constant throughout the life of the flash and change with retention. With retention, the distributions become larger and shift towards the erase level. The higher the distributions are the larger the shift. This effectively shrinks the effective working window. Both the shrinkage of the window and the fattening of the distributions contribute to the increase in number of errors after performing a page read. FIG. 2 illustrates these effects—the upper part of FIG. 2 includes eight non-overlapping lobes 301-308 that are positioned within a first window, the lower part of FIG. 2 illustrates overlapping lobes 311-318 that are positioned within a smaller window—the highest lobe is closer to the lowest lobe.
These effects become significantly worse as the block P/E cycles increase and as the NAND Flash memory technology node shrink.
The implications of the retention effect is that using the same set of read-thresholds just following a programming operation and then following retention time may contribute to the number of read errors.
FIG. 3 shows a typical prior art NAND FLASH string 30 and the reading circuitry 31 associated with it. A string is duplicated many times (say 34560 times) in a block and includes several (say 32) flash memory cells. Each of the flash memory cells is associated with a different wordline which connects all of the corresponding cells in the other strings of the block.
When a block is chosen, each string is connected to a corresponding bit-line by turning on the Bit Line Select and the Ground Select transistors. When a read operation is performed, a sense amplifier is connected to the bit-line and after allowing some time (say 25 uS) for the bit-line voltage to settle, the result is stored by a latch.
In order to measure the charge in a certain flash memory cell within a string, all other cells are switched on by applying a high voltage on their gates (given by Vbias) and a reference voltage Vref is applied to the gate of the selected cell. If the cell is charged and Vref is not high enough, the gate will not allow current to flow and the sense-amplifier will output a “0”. On the other hand, if the cell is not charge or Vref is high enough, current will flow and the sense-amplifier will output a “1”.
The above sampling technique holds when a bit may be obtained only through a single comparison (one bit per cell). When more than a single threshold comparison is required, the above procedure may be performed for each threshold and the results may then be combined.
Alternatively, several sense-amplifiers may be used simultaneously, and the current measured can be compared against multiple current thresholds—that are expected to distinguish between the threshold lobes.
Today's Flash devices will typically use a constant set of reference voltages that will minimized the number of errors as measured just following the programming procedure. However, such a choice will usually have an increased number of errors following a retention effect due to the lobe shift and widening effect.
The decoding capability following retention may be improved significantly, if on top of obtaining hard logical information per cell (“0” or “1”) we would also obtain some reliability information per each of these bits. The following invention presents methods for obtaining reliability information per bit using the same standard interface.